1. Field of the Invention
The present invention relates to a semiconductor apparatus in which a semiconductor chip is mounted on a substrate and a method of manufacturing the same.
2. Description of Related Art
A flip-chip ball grid array (FCBGA) has been known which electrically connects a semiconductor chip and a substrate where the semiconductor chip is mounted by a solder bump. In FCBGA, at reflow process (thermal treatment) for connecting the semiconductor chip and the substrate by a solder bump, a stress is generated between a semiconductor chip and a substrate, because they have different coefficients of thermal expansion. In FCBGA, the stress causes distortion. As a result, in FCBGA of a related art, bad soldering connection is likely to occur in a warped part at the time of mounting onto a circuit board. A semiconductor apparatus for reducing a stress which is generated due to a difference in coefficient of thermal expansion is disclosed in Japanese Unexamined Patent Application Publication No. 2004-260138, for example.
FIG. 6 shows a semiconductor apparatus 60 according to Japanese Unexamined Patent Application Publication No. 2004-260138. In the semiconductor apparatus 60, a semiconductor chip 63 is connected by flip-chip bonding onto a mounting substrate 61 with bump electrodes 62 interposed therebetween. A first resin 64 having a high coefficient of thermal expansion is formed in the space which is between the substrate 61 and the semiconductor chip 63. A second resin 65 having a lower coefficient of thermal expansion than the first resin 64 is formed in the space which is on the substrate 61 and surrounded by a covering portion 66 and the side surfaces of a reinforcing member 67 and the semiconductor chip 63.
In the semiconductor apparatus 60, a stress due to a difference in coefficient of thermal expansion between the semiconductor chip 63 and the substrate 61 is reduced by filling a resin having a high coefficient of thermal expansion between the semiconductor chip 63 and the substrate 61. Further, a shrinkage or expansion stress of the first resin 64 due to a temperature change is reduced by setting the coefficient of thermal expansion of the second resin 65 to be smaller than that of the first resin 64.
Japanese Unexamined Patent Application Publication No. 2000-200870 discloses a semiconductor apparatus in which a semiconductor chip is connected by flip-chip bonding onto a substrate with eutectic solders interposed therebetween. In this semiconductor apparatus, a resin is formed between the substrate and the semiconductor chip and in the vicinity of the outer edge of the semiconductor chip.
Japanese Unexamined Patent Application Publication No. 2000-315698 discloses a semiconductor package in which a resin is injected onto a substrate where a semiconductor package is mounted by flip-chip bonding by means of transfer molding.
However, in Japanese Unexamined Patent Application Publication No. 2004-260138, it is difficult to sufficiently prevent warpage caused by stresses on the semiconductor chip 63 and the substrate 61 where the semiconductor chip 63 is mounted. FIGS. 7A to 7C show stresses applied to the substrate 61 and the semiconductor chip 63, respectively. A stress fa is generated perpendicularly (upward in FIG. 7A) to the plane of the semiconductor chip 63. A stress fb is generated perpendicularly (downward in FIG. 7B) to the plane of the substrate 61, in the opposite direction to the stress fa. In this case, a combined stress fa′ which is a difference between the stress fa and the stress fb is generated perpendicularly (upward in FIG. 7C) to the plane of the semiconductor chip 63. A stress fb′ which is generated perpendicularly (downward in FIG. 7C) remains in an area 40 that is not affected by the stress fa. Accordingly, the stresses fa′ and fb′ are applied onto the semiconductor chip 63 and the substrate 61, respectively.
The semiconductor apparatus 60 is thereby distorted (FIG. 7C). Because of no consideration about balancing out a stress applied to the semiconductor chip 63 and a stress applied to the substrate 61 in the semiconductor apparatus 60, it is difficult to sufficiently prevent distortion of the semiconductor apparatus 60 as a whole. Specifically, if the second resin 65 is formed simply to fill the entire space surrounded by the side surfaces of the reinforcing member 67 and the semiconductor chip 63, the stresses do not balance out, thus failing to sufficiently prevent distortion of the semiconductor apparatus 60 as a whole.
Japanese Unexamined Patent Application Publication Nos. 2000-200870 and 2000-315698 do not address prevention of distortion of a semiconductor chip and a substrate caused by stresses.
Therefore, it has been difficult to sufficiently prevent distortion of a semiconductor chip and a substrate where the semiconductor chip is mounted which is caused by stresses in the semiconductor apparatus of related arts.